1. Field of the Invention
The present invention relates to a process for manufacturing a semiconductor device, and more specifically to a process for forming a capacitor incorporated in a semiconductor device.
2. Description of Related Art
At present, in semiconductor devices of this type having capacitors, a high integration density is demanded, as can be seen in DRAM (dynamic random access memory). In order to fulfill this demand, an area required for each memory cell in the DRAM has been extremely reduced. For example, in a 1MDRAM or 4MDRAM, a 0.8 .mu.m rule has been adopted in the semiconductor device design, and further, in a 16MDRAM, a 0.6 .mu.m rule has been adopted.
As mentioned above, the integration density is increased more and more, namely, a memory capacity is increased more and more in a semiconductor memory. However, in order to elevate the production efficiency and to lower a production cost, it is not allowed to increase the size of a semiconductor device chip. Because of this, how small a memory cell is formed, is an important problem to be solved on the semiconductor device.
However, if the area of the memory cell is reduced, the amount of electric charges stored in the memory cell correspondingly become small. Therefore, it has become difficult to realize a high integration density of memory cells and at the same time to ensure a necessary amount of electric charge stored in each memory cell.
Under the above mentioned circumstance, a memory cell having a trench capacitor and a memory cell having a stacked capacitor have been proposed and reduced in practice.
As compared with the memory cell having the trench capacitor, the memory cell having the stacked capacitor has an excellent soft-error resistance and an advantage in which no damage is given to a silicon substrate. Therefore, the stacked capacitor type memory cell is expected as next generation memory cell structure.
As the stacked capacitor, there is proposed a stacked capacitor formed by utilizing a HSG (hemi-spherical grain) technology. This type of stacked capacitor is constituted of a capacitor lower plate (storage node capacitor cell plate), a capacitor insulator film and a capacitor upper plate (common plate), the capacitor lower plate being electrically connected through a contact hole formed in an interlayer insulator film, to a MOSFET (metal-oxide-semiconductor field effect transistor) formed in a semiconductor substrate. In this case, a number of hemi-spherical grains are formed on a surface of storage electrode (capacitor lower plate), so that a surface area of the storage electrode is substantially increased, with the result that an increased capacitance is realized.
As one example of the HSG technology for forming concaves and convexes by hemi-spherical grains, Japan Patent Application Pre-examination Publication No. JP-A-5-110023 (an English abstract of which is available from the Japanese Patent Office and is incorporated by reference in its entirety into this application) proposes to deposit an amorphous silicon film through a natural oxide film on a silicon film, and to conduct a heat treatment to cause migration in a surface of the amorphous silicon film, so that a surface-roughed polysilicon film having a concave-convex upper surface is formed.
This JP-A-5-110023 is so featured in that the formation of the concaves and convexes formed by the HSG technology is limited to only a top surface of the polysilicon film, and therefore, the increase of the capacitance inevitably has certain limit.
On the other hand, Japanese Patent Application Pre-examination Publication No. JP-A-5-315543 (an English abstract of which is available from the Japanese Patent Office and is incorporated by reference in its entirety into this application) proposes a process for forming, by the HSG technology, concaves and convexes not only on a top surface of a capacitor lower plate but also on a side surface of the capacitor lower plate. In this proposed process, after an amorphous silicon film deposited by a CVD (chemical vapor deposition) process is patterned by a selective etching, the patterned amorphous silicon film is heat-treated in an inert gas or vacuum atmosphere, so that the amorphous silicon film is crystallized into a polysilicon film. According to this process, since the concaves and convexes are formed not only on the top surface of the capacitor lower plate but also on the side surface of the capacitor lower plate, a large capacitance can be advantageously obtained.
However, the experiments conducted by the co-inventors of the present application showed that, in the process disclosed by JP-A-5-315543, the processing temperature for growing the hemi-spherical silicon crystalline grains is as narrow as .+-.2.5.degree. C. Therefore, this process is not suitable to a mass production.
In order to eliminate this disadvantage, a so called a "crystal nucleation" has been proposed in which SiH.sub.4 or the like is irradiated to the top surface and the side surface of the amorphous silicon to form nuclei on these surfaces, and then, an annealing is conducted to form the concaves and convexes on the top surface and the side surface of the amorphous silicon. More specifically, in this "crystal nucleation", an amorphous silicon film is formed to electrically connect to a semiconductor device element such as a MOSFET formed in a semiconductor substrate, through a contact hole selectively formed through an interlayer insulator film, and the amorphous silicon film is patterned to form a capacitor lower plate. A natural oxide film remaining on a surface of the capacitor lower plate is removed by use of HF of the like, and thereafter, SiH.sub.4 is irradiated onto the capacitor lower plate within a reaction chamber which is maintained at a predetermined temperature. After irradiation of SiH.sub.4, an annealing is conducted for a predetermined length of time. Thus, there is obtained the capacitor lower plate having the concaves and convexes formed on not only the top surface but also the side surface in accordance with the HSG technology.
In the above mentioned "crystal nucleation" process, however, it was observed that, a crystal grows from a boundary between the capacitor lower plate film and the interlayer insulator film, and this crystallization reaches to the exposed top surface and the exposed side surface of the capacitor lower plate before the concaves and convexes are formed on the top surface and the side surface of the capacitor lower plate. If the crystallization reaches to the top surface and the side surface, the HSG formation process no longer advances, with the result that an expected increase of the surface area of the capacitor lower plate cannot be obtained. Actually, in the same wafer, some memory chips can obtain an expected increase of the surface area of the capacitor lower plate, but other memory chips cannot obtain the expected increase of the surface area of the capacitor lower plate, with the result that the production yield is low.